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CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36
Integrated Device Technology, Inc.
IDT723613
FEATURES:
* Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) * 64 x 36 storage capacity FIFO buffering data from Port A to Port B * Mailbox bypass registers in each direction * Dynamic Port B bus sizing of 36-bits (long word), 18-bits (word), and 9-bits (byte) * Selection of Big- or Little-Endian format for word and byte bus sizes * Three modes of byte-order swapping on Port B * Programmable Almost-Full and Almost-Empty flags * Microprocessor interface control logic * FF, AF flags synchronized by CLKA * EF, AE flags synchronized by CLKB * Passive parity checking on each Port
* * * * *
Parity Generation can be selected for each Port Low-power advanced BiCMOS technology Supports clock frequencies up to 67 MHz Fast access times of 10 ns Available in 132-pin quad flatpack (PQF) or space-saving 120-pin thin quad flatpack (TQFP) * Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications
DESCRIPTION:
The IDT723613 is a monolithic, high-speed, low-power, BiCMOS synchronous (clocked) FIFO memory which supports clock frequencies up to 67 MHz and has read-access times as fast as 10 ns. The 64 x 36 dual-port SRAM FIFO buffers data from port A to port B. The FIFO has flags to indicate empty and full conditions, and two programmable flags, Almost-Full (AF) and Almost-Empty (AE), to indicate
FUNCTIONAL BLOCK DIAGRAM
CLKA
W/RA ENA MBA
CSA
Port-A Control Logic Parity Gen/Check
Bus Matching and Output Byte Swapping Register
MBF1 PEFB
PGB
RST
ODD/
Mail 1 Register
Parity Generation
EVEN
36
Input Register
64 x 36 SRAM
Output Register
Device Control
36
64 x 36
Write Pointer
Read Pointer
B0 - B35
FF AF
FIFO
Status Flag Logic Programmable Flag Offset Registers
EF AE
CLKB Port-B Port-B Control Control Logic Logic
FS0 FS1 A0 - A35 PGA
CSB BE
W/RB ENB SIZ0 SIZ1 SW0 SW1
PEFA MBF2
Parity Gen/Check
Mail 2 Register
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The IDT logo is a registered trademark and SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
(c)1997 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
MAY 1997
DSC-3145/4
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IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
DESCRIPTION (CONTINUED)
when a selected number of words is stored in memory. FIFO data on port B can be output in 36-bit, 18-bit, and 9-bit formats with a choice of big- or little-endian configurations. Three modes of byte-order swapping are possible with any bus-size selection. Communication between each port can bypass the FIFO via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and may be ignored if not desired. Parity generation can be selected for data read from each port. Two or more devices may be used in parallel to create wider data paths. The IDT723613 is a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers
through a port are gated to the LOW-to-HIGH transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous interfaces. The Full Flag (FF) and Almost-Full (AF) flag of the FIFO are two-stage synchronized to the port clock (CLKA) that writes data into its array. The Empty Flag (EF) and Almost-Empty (AE) flag of the FIFO are two-stage synchronized to the port clock (CLKB) that reads data from its array. The IDT723613 is characterized for operation from 0C to 70C.
PIN CONFIGURATION
A24 A25 A26 VCC A27 A28 A29 GND A30 A31 A32 A33 A34 A35 GND B35 B34 B33 B32 B31 B30 GND B29 B28 B27 VCC B26 B25 B24 B23
A23 A22 A21 GND A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 GND A9 A8 A7 VCC A6 A5 A4 A3 GND A2 A1 A0 NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
B22 B21 GND B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 GND B9 B8 B7 VCC B6 B5 B4 B3 GND B2 B1 B0
EF AE
NC
ENA CLKA W/RA VCC PGA
SW1 SW0 SIZ1 SIZ0
MBA FS1 FS0 ODD/EVEN
MBF1 PEFB
PGB VCC W/RB CLKB ENB
AF FF CSA
GND
PEFA MBF2
RST BE
CSB
NC
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TQFP (PN120-1, order code: PF) TOP VIEW
NOTE: 1. NC = No internal connection
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IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION (CONTINUED)
MBA FS1 FS0 ODD/EVEN
ENA CLKA W/RA VCC PGA
PGB VCC W/RB CLKB ENB
MBF2
SW1 SW0 SIZ1 SIZ0
MBF1 GND PEFB
PEFA
GND
GND
AF FF CSA
RST
VCC A24 A25 A26 GND A27 A28 A29 VCC A30 A31 A32 GND A33 A34 A35 GND B35 B34 B33 GND B32 B31 B30 VCC B29 B28 B27 GND B26 B25 B24 VCC
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
GND NC NC A0 A1 A2 GND A3 A4 A5 A6 VCC A7 A8 A9 GND A10 A11 VCC A12 A13 A14 GND A15 A16 A17 A18 A19 A20 GND A21 A22 A23
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117
BE
NC NC
CSB
*
116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84
GND
AE EF
B0 B1 B2 GND B3 B4 B5 B6 VCC B7 B8 B9 GND B10 B11 VCC B12 B13 B14 GND B15 B16 B17 B18 B19 B20 GND B21 B22 B23
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* Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
PQFP
(2)
(PQ132-1, order code: PQF) TOP VIEW
NOTES: 1. NC = No internal connection. 2. Uses Yamaichi socket IC51-1324-828.
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IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Symbol A0-A35 Name Port A Data Almost-Empty Flag I/O Description I/O 36-bit bidirectional data port for side A. O Programmable almost-empty flag synchronized to CLKB. It is LOW when Port B Port B the number of 36-bit words in the FIFO is less than or equal to the value in the offset register, X. O Programmable almost-full flag synchronized to CLKA. It is LOW when the Port A number of 36-bit empty locations in the FIFO is less than or equal to the value in the offset register, X. I/O 36-bit bidirectional data port for side B I
AE AF
B0-B35
Almost-Full Flag
Port B Data Big-Endian Select
BE
CLKA
BE selects the most significant bytes on B0-B35 for use, and a HIGH selects
Selects the bytes on port B used during byte or word FIFO reads. A LOW on
Port A Clock
I
CLKB
Port B Clock
I
CSA CSB EF
Port A Chip Select
I
Port B Chip Select
I
Empty Flag
ENA ENB
Port A Enable Port B Enable Full Flag
FF
O EF is synchronized to the LOW-to-HIGH transition of CLKB. When EF is LOW, Port B the FIFO is empty, and reads from its memory are disabled. Data can be read from the FIFO to its output register when EF is HIGH. EF is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKB after data is loaded into empty FIFO memory. I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. O FF is synchronized to the LOW-to-HIGH transition of CLKA. When FF is LOW, Port A the FIFO is full, and writes to its memory are disabled. FF is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKA after reset. I The LOW-to-HIGH transition of RST latches the values of FS0 and FS1, which loads one of four preset values into the almost-full flag and almost-empty flag offsets. A high level on MBA chooses a mailbox register for a port A read or write operation. When the A0-A35 outputs are active, mail2 register data is output. MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1 register are inhibited while MBF1 is set LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a port B read is selected and both SIZ1 and SIZ0 are HIGH. MBF1 is set HIGH when the device is reset. MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2 register are inhibited while MBF2 is set LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a port A read is selected and MBA is HIGH. MBF2 is set HIGH when the device is reset.
the least significant bytes. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB. FF and AF are synchronized to the LOW-to-HIGH transition of CLKA. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or coincident to CLKA. Port-B byte swapping and data port sizing operations are also synchronous to the LOW-to-HIGH transition of CLKB. EF and AE are synchronized to the LOW-to-HIGH transition of CLKB. CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. The A0-A35 outputs are in the high-impedance state when CSA is HIGH. CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The B0-B35 outputs are in the high-impedance state when CSB is HIGH.
FS1, FS0
Flag Offset Selects
MBA
Port A Mailbox Select Mail1 Register Flag
I O
MBF1
MBF2
Mail2 Register Flag
O
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IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Symbol ODD/ Name Odd/Even Parity Select I/O I Description Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled for a read operation. When any byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the parity bit. The type of parity checked is determined by the state of the ODD/EVEN input. The parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if parity generation is selected by PGA. Therefore, if a mail2 read with parity generation is set up by having CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH and PGA HIGH, the PEFA flag is forced HIGH regardless of the state of the A0-A35 inputs. When any valid byte applied to terminals B0-B35 fails parity, PEFB is LOW. Bytes are organized as B0-B8, B9-B17, B-18-B26, and B27-B35, with the most significant bit of each byte serving as the parity bit. A byte is valid when it is used by the bus size selected for port B. The type of parity checked is determined by the state of the ODD/EVEN input. The parity trees used to check the B0-B35 inputs are shared by the mail1 register to generate parity if parity generation is selected by PGB. Therefore, if a mail1 read with parity generation is set up by having CSB LOW, ENB HIGH, W/RB LOW, SIZ1 and SIZ0 HIGH and PGB HIGH, the PEFB flag is forced HIGH regardless of the state of the B0-B35 inputs. Parity is generated for data reads from the mail2 register when PGA is HIGH. The type of parity generated is selected by the state of the ODD/EVEN input. Bytes are organized at A0-A8, A9-A17, A18-A26, and A27-A35. The generated parity bits are output in the most significant bit of each byte. Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26, and B27-B35. The generated parity bits are output in the most significant bit of each byte. To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-toHIGH transitions of CLKB must occur while RST is LOW. This sets the AF, MBF1, and MBF2 flags HIGH and the EF, AE, and FF flags LOW. The LOWto-HIGH transition of RST latches the status of the FS1 and FS0 inputs to select almost-full flag and almost-empty flag offset. A LOW-to-HIGH transition of CLKB latches the states of SIZ0, SIZ1, and BE, and the following LOW-to-HIGH transition of CLKB implements the latched states as a port B bus size. Port B bus sizes can be long word, word, or byte. A HIGH on both SIZ0 and SIZ1 accesses the mailbox registers for a port B 36-bit write or read. At the beginning of each long word FIFO read, one of four modes of byteorder swapping is selected by SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order swapping is possible with any bus-size selection. A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is HIGH. A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is HIGH.
EVEN PEFA
Port A Parity Error Flag
O (Port A)
PEFB
Port B Parity Error Flag
O (Port B)
PGA
Port A Parity Generation
I
PGB
Port B Parity
I
RST
Reset
I
SIZ0, SIZ1
Port B Bus Size Selects
I (Port B)
SW0, SW1
Port B Byte Swap Selects
I (Port B)
W/RA
Port A Write/Read Select Port B Write/Read Select
I
W/RB
I
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IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)(1)
Symbol VCC VI
(2) (2)
Rating Supply Voltage Range Input Voltage Range Output Voltage Range Input Clamp Current, (VI < 0 or VI > VCC) Output Clamp Current, (VO < 0 or VO > VCC) Continuous Output Current, (VO = 0 to VCC) Continuous Current Through VCC or GND Operating Free-Air Temperature Range Storage Temperature Range
Commercial -0.5 to 7 -0.5 to VCC+0.5 -0.5 to VCC+0.5 20 50 50 500 0 to 70 -65 to 150
Unit V V V mA mA mA mA C C
VO
IIK IOK IOUT ICC TA TSTG
NOTES: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIH VIL IOH IOL TA Parameter Supply Voltage High-Level Input Voltage Low-Level Input Voltage High-Level Output Current Low-Level Output Current Operating Free-Air Temperature 0 Min. Max. Unit 4.5 2 0.8 -4 8 70 5.5 V V V mA mA C
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
Parameter VOH VOL II IOZ ICC Ci Co VCC = 4.5V, VCC = 4.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VI = 0, VO = 0, Test Conditions IOH = -4 mA IOL = 8 mA VI = VCC or 0 VO = VCC or 0 IO = 0 mA, f = 1 MHz f = 1 MHz VI = VCC or GND 4 8 Min. 2.4 0.5 50 50 1 Typ.(1) Max. Unit V V A A mA pF pF
NOTE: 1. All typical values are at VCC = 5 V, TA = 25C.
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IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (SEE FIGURE 4 THROUGH 18)
Symbol fS tCLK tCLKH tCLKL tDS tENS tSZS tSWS tPGS tRSTS tFSS tDH tENH tSZH tSWH tPGH tRSTH tFSH tSKEW1
(3)
Parameter Clock Frequency, CLKA or CLKB Clock Cycle Time, CLKA or CLKB Pulse Duration, CLKA and CLKB HIGH Pulse Duration, CLKA and CLKB LOW Setup Time, A0-A35 before CLKA and B0-B35 before CLKB Setup Time, CSA, W/RA, ENA, and MBA before CLKA; CSB,W/RB, and ENB before CLKB Setup Time, SIZ0, SIZ1,and BE before CLKB Setup Time, SW0 and SW1 before CLKB Setup Time, ODD/EVEN and PGB before CLKB(1) Setup Time, RST LOW before CLKA or CLKB(2) Setup Time, FS0 and FS1 before RST HIGH Hold Time, A0-A35 after CLKA and B0-B35 after CLKB Hold Time, CSA W/RA, ENA and MBA after CLKA; CSB, W/RB, and ENB after CLKB Hold Time, SW0 and SW1 after CLKB Hold Time, ODD/EVEN and PGB after CLKB(1) Hold Time, RST LOW after CLKA or CLKB(2) Hold Time, FS0 and FS1 after RST HIGH Skew Time, between CLKA and CLKB for EF and FF
IDT723613L15 IDT723613L20 IDT723613L30 Min. Max. Min. Max. Min. Max. - 15 6 6 4 5 4 5 4 5 5 1 1 2 0 0 5 4 8 9 66.7 - - - - - - - - - - - - - - - - - - - - 20 8 8 5 5 5 7 5 6 6 1 1 2 0 0 6 4 8 16 50 - - - - - - - - - - - - - - - - - - - - 30 12 12 6 6 6 8 6 7 7 1 1 2 0 0 7 4 10 20 33.4 - - - - - - - - - - - - - - - - - - -
Unit MHz ns ns ns ns ns ns ns
ns ns ns ns ns ns ns ns ns ns ns
Hold Time, SIZ0, SIZ1, and BE after CLKB
tSKEW2(3) Skew Time, between CLKA and CLKB for AE and AF
NOTES: 1. Only applies for a clock edge that does a FIFO read. 2. Requirement to count the clock edge as one of at least four needed to reset a FIFO. 3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
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IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30pF (SEE FIGURE 4 THROUGH 18)
IDT723613L15 IDT723613L20 IDT723613L30 Min. Max. Min. Max. Min. Max. 2 2 2 2 2 1 10 10 10 10 10 9 2 2 2 2 2 1 12 12 12 12 12 12 2 2 2 2 2 1 15 15 15 15 15 15
Symbol tA tWFF tREF tPAE tPAF tPMF
Parameter Access Time, CLKA to A0-A35 and CLKB to B0-B35 Propagation Delay Time, CLKA to FF Propagation Delay Time, CLKB to EF
Unit ns ns ns ns ns ns
Propagation Delay Time, CLKB to AE Propagation Delay Time, CLKA to AF Propagation Delay Time, CLKA to MBF1 LOW or MBF2 HIGH and CLKB to MBF2 LOW or MBF1 HIGH Propagation Delay Time, CLKA to B0-B35(1) and CLKB to A0-A35(2) Propagation delay time, CLKB to PEFB Propagation Delay Time, SIZ1, SIZ0 to B0-B35 valid Propagation Delay Time, A0-A35 valid to PEFA valid; B0-B35 valid to PEFB valid
tPMR tPPE(3) tMDV tPDPE tPOPE tPOPB(4)
3 2 1 3 3 2
11 11 11 10 11 12
3 2 1 3 3 2
12 12 11.5 11 12 13
3 2 1 3 3 2
15 13 12 13 14 15
ns ns ns ns ns ns
Propagation Delay Time, ODD/EVEN to PEFA and PEFB
Propagation Delay Time, ODD/EVEN to parity bits (A8, A17, A26, A35) and (B8, B17, B26, B35) Propagation Delay Time, CSA, ENA, W/RA, MBA, or PGA to PEFA; CSB, ENB, W/RB, SIZ1, SIZ0, or PGB to PEFB
tPEPE
1
11
1
12
1
14
ns
tPEPB(4)
Propagation Delay Time, CSA, ENA, W/RA, MBA, or PGA to parity bits (A8, A17, A26, A35); CSB, ENB, W/RB, SIZ1, SIZ0, or PGB to parity bits (B8, B17, B26, B35) Propagation Delay Time, RST to AE, EF LOW and AF, MBF1, MBF2 HIGH
3
12
3
13
3
14
ns
tRSF tEN
1 2
15 10
1 2
20 12
1 2
25 14
ns ns
Enable Time, CSA and W/RA LOW to A0-A35 active and CSB LOW and W/RB HIGH to B0-B35 active Disable Time, CSA or W/RA HIGH to A0-A35 at high impedance and CSB HIGH or W/RB LOW to B0-B35 at high impedance
tDIS
1
8
1
9
1
11
ns
NOTES: 1. Writing data to the mail1 register when the B0-B35 outputs are active and SIZ1 and SIZ0 are HIGH. 2. Writing data to the mail2 register when the A0-A35 outputs are active. 3. Only applies when a new port-B bus size is implemented by the rising CLKB edge. 4. Only applies when reading data from a mail register.
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IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
RESET (RST) The IDT723613 is reset by taking the reset (RST) input LOW for at least four port A clock (CLKA) and four port B clock (CLKB) LOW-to-HIGH transitions. The reset input can switch asynchronously to the clocks. A device reset initializes the internal read and write pointers of the FIFO and forces the fullflag (FF) LOW, the empty flag (EF) LOW, the almost-empty flag (AE) LOW, and the almost-full flag (AF) HIGH. A reset also forces the mailbox flags (MBF1, MBF2) HIGH. After a reset, FF is set HIGH after two LOW-to-HIGH transitions of CLKA. The device must be reset after power up before data is written to its memory. A LOW-to-HIGH transition on the RST input loads the almost-full and almost-empty offset register (X) with the value selected by the flag select (FS0, FS1) inputs. The values that can be loaded into the register are shown in Table 1.
FIFO WRITE/READ OPERATION The state of the port A data (A0-A35) outputs is controlled by the port-A chip select (CSA) and the port-A write/read select (W/RA). The A0-A35 outputs are in the high-impedance state when either CSA or W/RA is HIGH. The A0-A35 outputs are active when both CSA and W/RA are LOW. Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is LOW, and FFA is HIGH (see Table 2). The state of the port B data (B0-B35) outputs is controlled by the port B chip select (CSB) and the port B write/read select (W/RB). The B0-B35 outputs are in the high-impedance state when either CSB or W/RB is HIGH. The B0-B35 outputs are active when both CSB and W/RB are LOW. Data is read from the FIFO to the B0-B35 outputs by a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, EFB is HIGH, and either SIZ0 or SIZ1 is LOW (see Table 3). The setup and hold-time constraints to the port clocks for the port chip selects (CSA, CSB) and write/read selects (W/ RA, W/RB) are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is LOW during a clock cycle, the port's chip select and write/read select can change states during the setup and hold time window of the cycle. SYNCHRONIZED FIFO FLAGS Each FIFO flag is synchronized to its port clock through two flip-flop stages. This is done to improve the flags' reliability by reducing the probability of metastable events on their outputs when CLKA and CLKB operate asynchronously to one another. FF and AF are synchronized to CLKA. EF and AE are synchronized to CLKB. Table 4 shows the relationship of each port flag to the level of FIFO fill.
TABLE 1: FLAG PROGRAMMING
FS1
FS0
RST

ALMOST-FULL AND ALMOST-EMPTY FLAG OFFSET REGISTER (X) 16 12 8 4
H H L L
H L H L
TABLE 2: PORT A ENABLE FUNCTION TABLE
CSA
H L L L L L L L
W/RA R X H H H L L L L
ENA X L H H L H L H
MBA X X L H L L H H
CLKA X X X X
A0-A35 OUPTUTS In high-impedance state In high-impedance state In high-impedance state In high impedence state Active, mail2 register Active, mail2 register Active, mail2 register Active, mail2 register
PORT FUNCTION None None FIFO write Mail1 write None None None Mail2 read (set MBF2 HIGH)
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IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
TABLE 3: PORT B ENABLE FUNCTION TABLE
CSB
H L L L L L L L
W/RB R X H H H L L L L
ENB X L H H L H L H
SIZ1, SIZ0 X X One, both LOW Both HIGH One, both LOW One, both LOW Both HIGH Both HIGH
CLKB X X X X
B0-B35 OUTPUTS In high-impedance state In high-impedance state In high-impedance state In high-impedance state Active, FIFO output regisger Active, FIFO output register Active, mail1 register Active mail1 register
PORT FUNCTION None None None Mail2 write None FIFO read None Mail1 read (set MBF1 HIGH)
EMPTY FLAG (EF EF) The FIFO empty flag is synchronized to the port clock that reads data from its array (CLKB). When the empty flag is HIGH, new data can be read to the FIFO output register. When the empty flag is LOW, the FIFO is empty and attempted FIFO reads are ignored. When reading the FIFO with a byte or word size on port B, EF is set LOW when the fourth byte or second word of the last long word is read. The FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine that controls the empty flag monitors a write-pointer and readpointer comparator that indicates when the FIFO SRAM status is empty, empty+1, or empty+2. A word written to the FIFO can be read to the FIFO output register in a minimum of three port B clock (CLKB) cycles. Therefore, an empty flag is LOW if a word in memory is the next data to be sent to the FIFO output register and two CLKB cycles have not elapsed since
the time the word was written. The empty flag of the FIFO is set HIGH by the second LOW-to-HIGH transition of CLKB, and the new data word can be read to the FIFO output register in the following cycle. A LOW-to-HIGH transition on CLKB begins the first synchronization cycle of a write if the clock transition occurs at time tSKEW1 or greater after the write. Otherwise, the subsequent CLKB cycle can be the first synchronization cycle (see Figure 9). FULL FLAG (FF FF) The FIFO full flag is synchronized to the port clock that writes data to its array (CLKA). When the full flag is HIGH, a SRAM location is free to receive new data. No memory locations are free when the full flag is LOW and attempted writes to the FIFO are ignored. Each time a word is written to the FIFO, its write-pointer is incremented. The state machine that controls the full flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is full, full-1, or full-2. From the time a word is read from the FIFO, its previous memory location is ready to be written in a minimum of three CLKA cycles. Therefore, a full flag is LOW if less than two CLKA cycles have elapsed since the next memory write location has been read. The second LOW-to-HIGH transition on the full flag synchronizing clock after the read sets the full flag HIGH and data can be written in the following clock cycle. A LOW-to-HIGH transition on CLKA begins the first synchronization cycle of a read if the clock transition occurs at time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figure 10). ALMOST-EMPTY FLAG (AE AE) The FIFO almost empty-flag is synchronized to the port clock that reads data from its array (CLKB). The state machine that controls the almost-empty flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is almost empty, almost empty+1, or almost
10
TABLE 4: FIFO FLAG OPERATION NUMBER OF 36-BIT WORDS IN THE FIFO (1) SYNCHRONIZED TO CLKB SYNCHRONIZED TO CLKA
EF
AE
L L H H H
AF
FF
0 1 to X (X+ 1) to [64 - (X + 1)] (64 - X) to 63 64
L H H H H
H H H L L
H H H H L
NOTE: 1. X is the value in the almost-empty flag and almost-full flag offset register
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
empty+2. The almost-empty state is defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with one of four preset values during a device reset (see reset above). The almost-empty flag is LOW when the FIFO contains X or less long words in memory and is HIGH when the FIFO contains (X+1) or more long words. Two LOW-to-HIGH transitions on the port B clock (CLKB) are required after a FIFO write for the almost-empty flag to reflect the new level of fill. Therefore, the almost-empty flag of a FIFO containing (X+1) or more long words remains LOW if two CLKB cycles have not elapsed since the write that filled the memory to the (X+1) level. The almost-empty flag is set HIGH by the second CLKB LOW-to-HIGH transition after the FIFO write that fills memory to the (X+1) level. A LOW-toHIGH transition of CLKB begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the write that fills the FIFO to (X+1) long words. Otherwise, the subsequent CLKB cycle can be the first synchronization cycle (see Figure 11). ALMOST FULL FLAG (AF AF) The FIFO almost-full flag is synchronized to the port clock that writes data to its array (CLKA). The state machine that controls an almost-full flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is almost full, almost full-1, or almost full-2. The almostfull state is defined by the value of the almost-full and almostempty offset register (X). This register is loaded with one of four preset values during a device reset (see reset above). The almost-full flag is LOW when the FIFO contains (64-X) or more long words in memory and is HIGH when the FIFO contains [64-(X+1)] or less long words. Two LOW-to-HIGH transitions on the port A clock (CLKA) are required after a FIFO read for the almost-full flag to reflect the new level of fill. Therefore, the almost-full flag of a FIFO containing [64-(X+1)] or less words remains LOW if two CLKA cycles have not elapsed since the read that reduced the number of long words in memory to [64-(X+1)]. The almostfull flag is set HIGH by the second CLKA LOW-to-HIGH transition after the FIFO read that reduces the number of long words in memory to [64-(X+1)]. A LOW-to-HIGH transition on CLKA begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the read that reduces the number of long words in memory to [64-(X+1)]. Otherwise, the subsequent CLKA cycle can be the first synchronization cycle (see Figure 12). MAILBOX REGISTERS Two 36-bit bypass registers (mail1, mail2) are on the IDT723613 to pass command and control information between port A and port B without putting it in queue. A LOW-toHIGH transition on CLKA writes A0-A35 data to the mail1 register when a port A write is selected by CSA, W/RA, and ENA (with MBA HIGH). A LOW-to-HIGH transition on CLKB writes B0-B35 data to the mail2 register when a port B write is selected by CSB, W/RB, and ENB (and both SIZ0 and SIZ1 are HIGH). Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while its mail flag is LOW. When the port B data (B0-B35) outputs are active, the
data on the bus comes from the FIFO output register when either one or both SIZ1 and SIZ0 are LOW and from the mail1 register when both SIZ1 and SIZ0 are HIGH. The mail1 register flag (MBF1) is set HIGH by a rising CLKB edge when a port B read is selected by CSB, W/RB, and ENB, (and both SIZ1 and SIZ0 HIGH). The mail2 register flag (MBF2) is set HIGH by a rising CLKA edge when a port A read is selected by CSA, W/RA, and ENA (with MBA HIGH). The data in a mail register remains intact after it is read and changes only when new data is written to the register. DYNAMIC BUS SIZING The port B bus can be configured in a 36-bit long word, 18-bit word, or 9-bit byte format for data read from the FIFO. Word- and byte-size bus selections can utilize the most significant bytes of the bus (big endian) or least significant bytes of the bus (little endian). Port B bus-size can be changed dynamically and synchronous to CLKB to communicate with peripherals of various bus widths. The levels applied to the port B bus-size select (SIZ0, SIZ1) inputs and the big-endian select (BE) input are stored on each CLKB LOW-to-HIGH transition. The stored port B bus-size selection is implemented by the next rising edge on CLKB according to Figure 1. Only 36-bit long-word data is written to or read from the FIFO memory on the IDT723613. Bus-matching operations are done after data is read from the FIFO RAM. Port B bus sizing does not apply to mail register operations. BUS-MATCHING FIFO READS Data is read from the FIFO RAM in 36-bit long-word increments. If a long-word bus-size is implemented, the entire long word immediately shifts to the FIFO output register upon a read. If byte or word size is implemented on port B, only the first one or two bytes appear on the selected portion of the FIFO output register, with the rest of the long word stored in auxiliary registers. In this case, subsequent FIFO reads with the same bus-size implementation output the rest of the long word to the FIFO output register in the order shown by Figure 1. Each FIFO read with a new bus-size implementation automatically unloads data from the FIFO RAM to its output register and auxiliary registers. Therefore, implementing a new port B bus-size and performing a FIFO read before all bytes or words stored in the auxiliary registers have been read results in a loss of the unread data in these registers. When reading data from FIFO in byte or word format, the unused B0-B35 outputs remain inactive but static, with the unused FIFO output register bits holding the last data value to decrease power consumption. BYTE SWAPPING The byte-order arrangement of data read from the FIFO can be changed synchronous to the rising edge of CLKB. Byte-order swapping is not available for mail register data. Four modes of byte-order swapping (including no swap) can be done with any data port size selection. The order of the bytes are rearranged within the long word, but the bit order within the bytes remaines constant.
11
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
A35 A27
BYTE ORDER ON PORT A:
A26 A18
A17 A9
A8
A0 Write to FIFO
A
B
B26 B18
C
B17 B9
D
B8
BE
X
B35 B27 SIZ1 SIZ0 L L
B0 Read from FIFO
A
B
(a) LONG WORD SIZE
C
D
B35 B27
B26 B18
B17 B9
B8
B0 1st: Read from FIFO
BE
L
SIZ1 SIZ0 L H
A
B35 B27
B
B26 B18 B17 B9 B8
B0 2nd: Read from FIFO
C
D
(b) WORD SIZE -- BIG ENDIAN
BE
H
B35 B27 SIZ1 L SIZ0 H B35 B27
B26 B18
B17
B9
B8
B0 1st: Read from FIFO B0 2nd: Read from FIFO
C
B26 B18 B17 B9
D
B8
A
(c) WORD SIZE -- LITTLE ENDIAN
B
BE
L
B35 B27 SIZ1 SIZ0 H L
B26 B18
B17
B9
B8
B0 1st: Read from FIFO
A
B35 B27 B26 B18 B17 B9 B8
B0 2nd: Read from FIFO
B
B35 B27 B26 B18 B17 B9 B8
B0 3rd: Read from FIFO
C
B35 B27 B26 B18 B17 B9 B8
B0 4th: Read from FIFO
D
(d) BYTE SIZE -- BIG ENDIAN
Figure 1. Dynamic Bus Sizing
3145 fig 01
12
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
BE
H
B35 B27 SIZ1 SIZ0 H L B35 B27
B26 B18
B17 B9
B8
B0
D
B26 B18 B17 B9 B8 B0
1st: Read from FIFO
C
A35 A27 A26 A18 A17 A9 A8 A0
2nd: Read from FIFO
B
B35 B27 B26 B18 B17 B9 B8
3rd: Read from FIFO B0
A
(d) BYTE SIZE -- LITTLE ENDIAN
4th: Read from FIFO
3145 drw fig 01a
Figure 1. Dynamic Bus Sizing (continued)
Byte arrangement is chosen by the port B swap select (SW0, SW1) inputs on a CLKB rising edge that reads a new long word from the FIFO. The byte order chosen on the first byte or first word of a new long word read from the FIFO is maintained until the entire long word is transferred, regardless of the SW0 and SW1 states during subsequent reads. Figure 3 is an example of the byte-order swapping available for long word reads. Performing a byte swap and bus-size simulationeously for a FIFO read first rearranges the bytes as shown in Figure 3, then outputs the bytes as shown in Figure 1.
PORT-B MAIL REGISTER ACCESS In addition to selecting port B bus sizes for FIFO reads, the port B bus size select (SIZ0, SIZ1) inputs also access the mail registers. When both SIZ0 and SIZ1 are HIGH, the mail1 register is accessed for a port B long-word read and the mail2 register is accessed for a port B long-word write. The mail register is accessed immediately and any bus-sizing operation that can be underway is unaffected by the mail register access. After the mail register access is complete, the previous FIFO access can resume in the next
CLKB
G1 1 SIZ0 SIZ1
MUX
BE
**
1
D
Q
*
*
*
SIZ0 Q SIZ1 Q BE Q
3145 drw fig 02
Figure 2. Logic Diagram for SIZ0, SIZ1, and BE Register
13
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
A35 A27 SW1 L L SW0 L L
A26 A18
A17 A9
A8
A0
A
B
C
D
A
B35 B27 A35 A27 SW1 L SW0 H
B
B26 B18 A26 A18
(a) NO SWAP
C
B17 B9
D
B8 A8 B0 A0
A17 A9
A
B
C
D
D
B35 B27
C
B26 B18
(b) BYTE SWAP
B
B17 B9
A
B8 B0
A35 A27 SW1 H SW0 L
A26 A18
A17 A9
A8
A0
A
B
C
D
C
B35 B27 A35 A27 SW1 H SW0 H
D
B26 B18 A26 A18
(c) WORD SWAP
A
B17 B9
B
B8 A8 B0 A0
A17 A9
A
B
C
D
B
B35 B27
A
B26 B18
D
B17 B9
C
B8 B0
(d) BYTE-WORD SWAP
3145 drw fig 03
Figure 3. Byte Swapping for FIFO Reads (Long-Word Size Example)
14
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
CLKB cycle. The logic diagram in Figure 2 shows the previous bus-size selection is preserved when the mail registers are accessed from port B. A port B bus-size is implemented on each rising CLKB edge according to the states of SIZ0_Q, SIZ1_Q, and BE_Q. PARITY CHECKING The port A data inputs (A0-A35) and port B data inputs (B0B35) each have four parity trees to check the parity of incoming (or outgoing) data. A parity failure on one or more bytes of the port A data bus is reported by a low level on the port A parity error flag (PEFA). A parity failure on one or more bytes of the port B data inputs that are valid for the bus-size implementation is reported by a low level on the port B parity error flag (PEFB). Odd or even parity checking can be selected, and the parity error flags can be ignored if this feature is not desired. Parity status is checked on each input bus according to the level of the odd/even parity (ODD/EVEN) select input. A parity error on one or more valid bytes of a port is reported by a LOW level on the corresponding port-parity-error flag (PEFA, PEFB) output. Port A bytes are arranged as A0-A8, A9-A17, A18A26, and A27-A35, and port B bytes are arranged as B0-B8, B9-B17, B18-B26, and B27-B35, and its valid bytes are those used in a port B bus size implementation. When odd/even parity is selected, a port-parity-error flag (PEFA, PEFB) is LOW if any byte on the port has an odd/even number of LOW levels applied to its bits. The four parity trees used to check the A0-A35 inputs are shared by the mail2 register when parity generation is selected for port-A reads (PGA = HIGH). When a port A read from the mail2 register with parity generation is selected with CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA HIGH, the port A parity error flag (PEFA) is held HIGH regardless of the levels applied to the A0-A35 inputs. Likewise, the parity trees used to check the B0-B35 inputs are shared by the mail1 register when parity generation is selected for port B reads (PGB = HIGH). When a port B read from the mail1 register with parity generation is selected with CSB LOW, ENB HIGH, W/RB LOW, both SIZ0 and SIZ1 HIGH, and
PGB HIGH, the port B parity error flag (PEFB) is held HIGH regardless of the levels applied to the B0-B35 inputs. PARITY GENERATION A HIGH level on the port A parity generate select (PGA) or port B generate select (PGB) enables the IDT723613 to generate parity bits for port reads from a FIFO or mailbox register. Port A bytes are arranged as A0-A8, A9-A17, A18A26, and A27-A35, with the most significant bit of each byte used as the parity bit. Port B bytes are arranged as B0-B8, B9B17, B18-B26, and B27-B35, with the most significant bit of each byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all nine inputs of a byte regardless of the state of the parity generate select (PGA, PGB) inputs. When data is read from a port with parity generation selected, the lower eight bits of each byte are used to generate a parity bit according to the level on the ODD/ EVEN select. The generated parity bits are substituted for the levels originally written to the most significant bits of each byte as the word is read to the data outputs. Parity bits for FIFO data are generated after the data is read from SRAM and before the data is written to the output register. Therefore, the port A parity generate select (PGA) and odd/even parity select (ODD/EVEN) have setup and hold time constraints to the port A clock (CLKA) and the port B parity generate select (PGB) and ODD/EVEN select have setup and hold time constraints to the port B clock (CLKB). These timing constraints only apply for a rising clock edge used to read a new long word to the FIFO output register. The circuit used to generate parity for the mail1 data is shared by the port B bus (B0-B35) to check parity and the circuit used to generate parity for the mail2 data is shared by the port A bus (A0-A35) to check parity. The shared parity trees of a port are used to generate parity bits for the data in a mail register when the port chip select (CSA, CSB) is LOW, enable (ENA, ENB) is HIGH, and write/read select (W/RA, W/RB) input is LOW, the mail register is selected (MBA HIGH for port A; both SIZ0 and SIZ1 are HIGH for port B), and port parity generate select (PGA, PGB) is HIGH. Generating parity for mail register data does not change the contents of the register.
15
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
CLKA tRSTH CLKB tRSTS tFSS tFSH
RST
FS1,FS0 0,1 tWFF tWFF
FF EF AE AF MBF1, MBF2
tRSF
tREF
tPAE
tPAF
3145 drw 04
Figure 4. Device Reset Loading the X Register with the Value of Eight
tCLK tCLKH CLKA tCLKL
FFA CSA
W/RA
(HIGH)
tENS tENS
tENH tENH
tENS MBA tENS ENA tDS A0 - A35 ODD/ W1 (1)
tENH
tENH tDH
tENS
tENH
tENS
tENH
W2 (1)
No Operation
EVEN PEFA
NOTE: 1. Written to the FIFO.
tPDPE Valid
tPDPE Valid
3145 drw 05
Figure 5. FIFO Write Cycle Timing
16
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
CLKB
EF CSB
W/RB
HIGH
tENS ENB tSWS SW1, SW0 tSZS tSZS SIZ1, SIZ0 PGB, ODD/ (0,0)
tENH tSWH
tENS No Operation
tENH
BE
tSZH tSZH NOT (1,1)(1) tPGS tEN (0,0) tPGH tA Previous Data tA W1(2) tDIS W2 (2)
3146 drw 06
NOT (1,1)(1)
EVEN
B0-B35
NOTES: 1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35. 2. Data read from FIFO1.
DATA SWAP TABLE FOR FIFO LONG-WORD READS FIFO DATA WRITE A35-A27 A A A A A26-A18 B B B B A17-A9 C C C C A8-A0 D D D D SWAP MODE SW1 L L H H SW0 L H L H FIFO DATA READ B35-B27 B26-B18 A D C B B C D A B17-B9 C B A D B8-B0 D A B C
Figure 6. FIFO Long-Word Read Cycle Timing
17
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
CLKB
EF CSB
W/RB
HIGH
tENS ENB tSWS SW1, SW0 tSZS tSZS SIZ1, SIZ0 PGB, ODD/ (0,1)
tENH tSWH No Operation
BE
tSZH tSZH NOT (1,1)(1) tPGS tEN (0,1) tPGH tA Previous Data tA Previous Data tA Read 1 tA Read 1 tDIS Read 2 tDIS Read 2
3145 drw 07
NOT (1,1)(1)
EVEN
Little Endian (2) Big Endian (2)
B0-B17 B18-B35
NOTES; 1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35. 2. Unused word B0-B17 or B18-B35 holds last FIFO1 output register data for word-size reads.
DATA SWAP TABLE FOR FIFO WORD READS
FIFO DATA WRITE A35-A27 A A26-A18 B A17-A9 C A8-A0 D SWAP MODE SW1 L SW0 L 1 2 1 2 1 2 1 2 READ NO. FIFO DATA READ BIG ENDIAN B35-B27 B26-B18 A B C D D B C A B D C A D B A C LITTLE ENDIAN B17-B9 C A B D A C D B B8-B0 D B A C B D C A
A
B
C
D
L
H
A
B
C
D
H
L
A
B
C
D
H
H
Figure 7. FIFO Word Read-Cycle Timing
18
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
CLKB
EF CSB
W/RB
HIGH
tENS ENB tSWS SW1, SW0 tSZS tSZS SIZ1, SIZ0 PGB, ODD/ EVEN B0-B8 (1,0) Not (1,1) tPGS tEN
(1)
tENH tSWH No Operation
BE
tSZH tSZH (1,0) tPGH tA Read 1 tA Read 1 tA Read 2 tA Read 2 tA Read 3 tA Read 3 tDIS Read 4 tDIS Read 4
3145 drw 08
(1,0) Not (1,1)
(1)
(1,0) Not (1,1)
(1)
Not (1,1) (1)
tA Previous Data tA
B27-B35
Previous Data
NOTES: 1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35. 2. Unused bytes hold last FIFO output register data for byte-size reads.
DATA SWAP TABLE FOR FIFO BYTE READS
FIFO DATA READ FIFO DATA WRITE A35-A27 A26-A18 A17-A9 A8-A0 SWAP MODE SW1 SW0 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 READ NO. BIG ENDIAN B35-B27 A B C D D C B A C D A B B A D C LITTLE ENDIAN B8-B0 D C B A A B C D B A D C C D A B
A
B
C
D
L
L
A
B
C
D
L
H
A
B
C
D
H
L
A
B
C
D
H
H
Figure 8. FIFO Byte Read-Cycle Timing
19
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
tCLKH CLKA
tCLK tCLKL
CSA
LOW tENS tENS tENH tENH
WRA HIGH MBA ENA
FF
A0 - A35
HIGH
tDS W1
tDH
tSKEW1 (1) CLKB
tCLKH 1
tCLK tCLKL 2 tREF tREF
EF CSB
LOW
FIFO Empty
W/RB LOW SIZ1, SIZ0 LOW ENB tA B0 -B35 W1
3145 drw 09
tENS
tENH
NOTES: 1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown. 2. Port B size of long word is selected for the FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port-B size is word or byte, EF is set LOW by the last word or byte read from the FIFO, respectively. Figure 9. EF Flag Timing and First Data Read when the FIFO is Empty
20
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
tCLK tCLKH CLKB tCLKL
CSB
W/RB SIZ1, SIZ0 ENB
LOW LOW LOW tENS tENH
EF
B0 -B35
HIGH tA
Previous Word in FIFO Output Register Next Word From FIFO
tSKEW1(1) tCLKH CLKA 1 FIFO Full LOW HIGH
tCLK tCLKL 2 tWFF tWFF
FF CSA
WRA MBA
tENS tENS
tENH tENH tDH
To FIFO
3145 drw 10
ENA tDS A0 - A35
NOTES: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKA cycle later than shown. 2. Port B size of long word is selected for the FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively. Figure 10. FF Flag Timing and First Available Write when the FIFO is Full
21
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
CLKA tENS ENA tSKEW2 CLKB
(1)
tENH
1
2 tPAE tPAE
(X+1) Long Words in FIFO
AE
ENB
X Long Words in FIFO
tENS
tENH
3145 drw 11
NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown. 2. FIFO write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = LOW, MBB = LOW). 3. Port B size of long word is selected for the FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW2 is referenced to the last word or byte of the long word, respectively.
Figure 11. Timing for AE when the FIFO is Almost Empty
tSKEW2 CLKA tENS ENA tPAF tENH
(1)
1
2
tPAF
(64-X) Long Words in FIFO
AF
CLKB
[64-(X+1)] Long Words in FIFO
tENS ENB
tENH
3145 drw 12
NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKB cycle later than shown. 2. FIFO write (CSA = L0W, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = LOW, MBB = LOW). 3. Port-B size of long word is selected for FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW2 is referenced from the last word or byte read of the long word, respectively. Figure 12. Timing for AF when the FIFO is Almost Full
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IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
CLKA tENS tENH
CSA
W/RA MBA ENA A0 - A35 tDS W1 tDH
CLKB
MBF1 CSB
W/RB SIZ1, SIZ0
tPMF
tPMF
tENS ENB tEN B0 - B35 FIFO Output Register
NOTE: 1. Port-B parity generation off (PGB = LOW). Figure 13. Timing for Mail1 Register and MBF1 Flag
tENH
tMDV tPMR
tDIS W1 (Remains valid in Mail1 Register after read)
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23
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
CLKB tENS
tENH
CSB
W/RB SIZ1, SIZ0 ENB tDS W1 tDH tSZS tENS tSZH tENH
B0 - B35
CLKA
MBF2 CSA
W/RA MBA
tPMF
tPMF
tENS ENA tEN A0 - A35
NOTE: 1. Port-A parity generation off (PGA = LOW). Figure 14. Timing for Mail2 Register and MBF2 Flag
tENH
tPMR
tDIS W1 (Remains valid in Mail2 Register after read)
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IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
ODD/
EVEN
W/RA MBA PGA tPOPE tPOPE Valid Valid tPEPE tPEPE Valid
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PEFA
Valid
NOTE: 1. CSA = LOW and ENA = HIGH.
Figure 15. ODD/EVEN W/RA, MBA, and PGA to PEFA Timing EVEN, R
ODD/
EVEN
W/RB SIZ1, SIZ0 PGB tPOPE tPOPE Valid Valid
tPEPE
tPEPE Valid
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PEFB
Valid
NOTE: 1. CSB = LOW and ENB = HIGH. Figure 16. ODD/EVEN W/RB, SIZ1, SIZ0, and PGB to PEFB Timing EVEN, R
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IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
ODD/
EVEN CSA
W/RA MBA PGA
LOW
tEN A8, A17, A26, A35
NOTE: 1. ENA = HIGH.
tPEPB Mail2 Data
tPOPB Generated Parity
tPEPB Generated Parity
Mail2 Data
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Figure 17. Parity Generation Timing when Reading from the Mail2 Register
ODD/
EVEN CSB
W/RB SIZ1, SIZ0 PGB
LOW
tEN B8, B17, B26, B35
NOTE: 1. ENB = HIGH.
tPEPB tMDV Mail1 Data
tPOPB Generated Parity
tPEPB Generated Parity Mail1 Data
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Figure 18. Parity Generation Timing when Reading from the Mail1 Register
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IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
TYPICAL CHARACTERISTICS
SUPPLY CURRENT vs CLOCK FREQUENCY 400
350
f data = 1/2 f s T A = 25 C C L = 0 pF
VCC = 5.5 V
300
ICC(f) - Supply Current - mA
250
VCC = 5 V
200
VCC = 4.5 V
150
100
50
0 0 10 20 30 40 50 60 70 80
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f s - Clock Frequency - MHz
FIGURE 19
CALCULATING POWER DISSIPATION The ICCf current for the graph in Figure 19 was taken while simultaneously reading and writing the FIFO on the IDT723613 with CLKA and CLKB set to fs. All date inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero-copacitance load. Once the capacitive lead per data-output channel is known, the power dissipation can be calculated with the equation below. With ICC(f) taken from Figure 19, the maximum power dissipation (PT) of the IDT723613 may be calculated by: PT = VCC x ICC(f) + [CL x (VOH - VOL)2 x fO) where: = CL fo = VOH VOL = = output capacitive load switching frequency of an output output high-level voltage output high-level voltage
When no reads or writes are occurring on the IDT723613, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fs is calculated by: PT = VCC x fs x 0.29ma/MHz
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IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
PARAMETER MEASUREMENT INFORMATION
5V
1.1 k From Output Under Test 680 30 pF
(1)
PROPAGATION DELAY LOAD CIRCUIT
3V Timing Input tS Data, Enable Input 1.5 V 1.5 V GND th 3V 1.5 V GND Low-Level Input 1.5 V High-Level Input 1.5 V tW 1.5 V
3V GND 3V 1.5 V GND
VOLTAGE WAVEFORMS SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS PULSE DURATIONS
Output Enable tPLZ Low-Level Output
3V 1.5 V 1.5 V tPZL 1.5 V tPZH 1.5 V VOL VOH In-Phase Output GND 3 V Input 3V 1.5 V tPD 1.5 V 1.5 V GND tPD VOH 1.5 V VOL
High-Level Output
tPHZ
OV
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
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NOTE: 1. Includes probe and jig capacitance.
Figure 20. Load Circuit and Voltage Waveforms
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IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXXX Device Type X Power XX Speed X Package X Process/ Temperature Range
BLANK
Commercial (0C to +70C)
PF PQF 15 20 30
Thin Quad Flat Pack (TQFP, PN120-1) Plastic Quad Flat Pack (PQFP, PQ132-1) Commercial Only Clock Cycle Time (tCLK) Speed in Nanoseconds
L
Low Power
723613
64 x 36 Synchronous FIFO
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